1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same. More particularly, the invention relates to a semiconductor device including a multilevel wiring which uses a low dielectric constant insulating film, and a method for manufacturing the same.
2. Description of the Related Art
A semiconductor device, especially a recent semiconductor device such as a system LSI or a DRAM in which miniaturization and high-integration of a semiconductor integrated circuit have progressed, uses a microfabricated multilevel wiring. Accordingly, there is a strong demand for improving wiring performance in order to achieve a higher speed operation. In particular, suppression of a wiring delay caused by wiring resistance (R) and a wiring capacitance (C) is an important task to realize the higher speed operation. The wiring delay is represented by a product of wiring resistance and wiring capacitance (=R×C). Thus, in development of multilevel wirings, in order to suppress a wiring delay, it is one of the important tasks to reduce a wiring capacitance by lowering resistance of the wiring material and lowering dielectric constant of an interwiring or interlevel insulating film. As no practical and proper low-resistant materials other than copper are found as acceptable wiring materials, it is apparently difficult to achieve lowering wiring resistance further. Thus, an interlevel insulating film with a lower dielectric constant material is preferably used to reduce the wiring capacitance.
However, such a low dielectric constant insulating film generally is weak in mechanical strength in nature. Consequently, problems are inherent in a manufacturing process of the semiconductor device, for example, easy to form an deteriorated layer in a surface of the low dielectric constant insulating film, and easy to cause damages such as a scratch.
FIG. 24 is a sectional view showing an example of a copper (Cu) wiring according to a conventional technology. For example, an isolation, a metal-oxide semiconductor field effect transistor (MOSFET), and the like are formed in a semiconductor (e.g., silicon) substrate. To simplify explanation, such components are omitted here, and only a wiring structure formed on the semiconductor substrate is shown. As shown in FIG. 24, a low dielectric constant insulating film 911 having a dielectric constant lower than that of a silicon oxide (SiO2) film is formed as an interwiring insulating film on entire surface of the silicon substrate (not shown), and a high-strength insulating film 912 having a mechanical strength higher than that of the low dielectric constant insulating film 911 is formed thereon. For example, an SiO2 film is used as the high-strength insulating film 912. Next, a wiring trench is formed in the low dielectric constant insulating film 911 and the high-strength insulating film 912 by means of lithography and etching. A Cu film is formed on the entire surface over a Cu diffusion preventing barrier metal film 915 to fill the wiring trench. For example, a tantalum nitride (TaN) is used for the Cu diffusion preventing barrier metal film 915. Then, the Cu film formed in a region other than the wiring trench is removed by chemical mechanical polishing (CMP) to form a Cu wiring 917 in the wiring trench. Then, a Cu diffusion preventing barrier insulating film 919 is formed on the entire surface. For example, an SiN film is used as the Cu diffusion preventing barrier insulating film 919. Thus, the conventional semiconductor device has a structure in which the low dielectric constant insulating film 911, the high-strength insulating film 912, and the Cu diffusion preventing barrier insulating film 919 are alternately stacked. Relative permittivity of the high-strength insulating film 912 and the Cu diffusion barrier insulating film 919 are generally larger than that of the low dielectric constant insulating film 911. Therefore, an overall relative permittivity of the interwiring and interlevel insulating films becomes larger than that of the low dielectric constant insulating film 911.
When a semiconductor device is manufactured by using the low dielectric constant insulating film 911 as the interwiring or interlevel insulating film without using the high-strength insulating film 912 made of SiO2, processing damage should be introduced in the surface of the low dielectric constant insulating film 911 exposed to the surface in the manufacturing process. For example, when a wiring trench or the like is formed in the low dielectric constant insulating film 911 by reactive ion etching (RIE), processing damage may be introduced in the surface thereof due to RIE. Alternatively, when the Cu film formed in the region other than the wiring trench is removed by CMP to leave the Cu wiring 917 in the wiring trench, polishing damage may be introduced in the surface of the low dielectric constant insulating film 911. Such damage will cause problems, for example, an increase in leakage current between the wirings or the wiring levels.
As described above, according to the conventional method, the high-strength insulating film 912 made of SiO2 is used as a kind of protective film to prevent processing damage to the low dielectric constant insulating film 911 therebelow, and not removed in the process. Additionally, the Cu diffusion preventing barrier insulating film 919 of SiN formed on the Cu wiring 917 is not removed from portions other than a contact of the Cu wiring 917 mostly. Consequently, the high-strength insulating film (SiO2) 912 and the Cu diffusion preventing barrier insulating film (SiN) 919 of relative permittivity larger than that of the low dielectric constant insulating film 911 are left in the completed semiconductor device. In other words, when a multilevel wiring is formed by such a method, the multilevel wiring has a laminated structure of a low dielectric constant insulating film and a high dielectric constant insulating film as the interwiring and interlevel insulating films. Thus, in the multilevel wiring formed by the conventional method, while it can be suppressed processing damage caused by RIE, CMP or the like in the surface of the insulating film, there is a problem to suppress an operation delay in a semiconductor device sufficiently because of a larger wiring capacitance compared with that in the case of using only the low dielectric constant insulating film for the interwiring and interlevel insulating film.